CEA LIST
Division of Architecture & IC Design, Embedded Software
Embedded Computing Laboratory
CEA Nano-Innov
PC172
91191 Gif-sur-Yvette CEDEX - FRANCE
Phone: (+33) 169-085-543
Fax: (+33) 169-088-895
Email: nicolas.ventroux@cea.fr View Nicolas VENTROUX's profile
Research Interests
I am interested in the design of parallel and multithreaded architectures, multi and many-core architectures, reconfigurable and auto-adaptive architectures.
In particular, I have focused my research on multiprocessor modeling and exploration (TLM, SystemC), energy consumption management, reliability and fault-tolerant systems.
Currently, I am leading the development around the SCMP multiprocessor architecture and a multiprocessor simulation environment named SESAM.
Short Bio
Nicolas Ventroux is a research engineer in the Embedded Computing Laboratory at CEA LIST.
He received a M.Sc and a M.Eng. in Computer Sciences from INSA, Rennes in 2003, and the PhD degree in Electronics from the University of Rennes in 2006.
Today, He is a CEA expert in multiprocessor modeling and design, and a project manager of national and European projects.
He wrote, as author and co-author, six patents and several papers in conferences and journals about multicore and manycore architectures, virtual prototyping,
multicore scheduling strategies, reliability, stereovision and image processing, as well as multithreaded, reconfigurable and auto-adaptive architectures.
In particular, He designed a virtual prototyping solution named SESAM and managed the complete design of a hardware multiprocessor platform called SCMP.
SCMP is an asymmetric multicore architecture dedicated to dynamic applications for embedded systems. It supports a dynamic scheduling of tasks under real-time
and energy consumption constraints. He is also a reviewer for several international conferences and journals since 2006.
Handling design issues related to reliability in MPSoC at functional level
Tushar Gupta
University of Bordeaux 1, December 2011
Study and design of a manycore architecture with multithreaded processors for dynamic embedded applications
Charly Bechara
University of Paris-Sud, December 2011
Test en ligne pour la détection des fautes intermittentes dans les architectures multiprocesseurs embarquées(pdf)
Online self-testing for intermittent faults detection in embedded multiprocessor architectures
Julien Guilhemsang
University of Nice-Sophia Antipolis, April 2011
Approche hiérarchique pour la gestion dynamique des tâches et des communications dans les architectures massivement parallèles programmables(pdf)
Hierarchical approach for the dynamic tasks and communications management in massive programmable parallel architectures
Alexandre Guerre
University of Paris 11, September 2010
Past Undergraduate/Master students
Guanglin Xu, "Checkpointing on SystemC", Sun Yat-Sen University, 2012 (3 months)
Dennis Liang, "Integration of GenIssLib into the SESAM framework", Carnegie Mellon University, ECE, 2012 (3 months)
Aurélien Berhault, "design of a light multithreaded processor for embedded systems", ENSEIRB, 2011 (7 months)
Julien Peeters, "design of a software prototype for many-core architectures", University of Paris 6, 2010 (6 months)
Tanguy Sassolas, "Design of a multicore architecture", ENSEEIHT, 2008 (6 months)
Nathalie Gobet, "Design of a simulator for multiprocessor architectures", ENSEIRB, 2007 (6 months)
Jean-Loup Leroy, "Study of a real-time operating system in multiprocessor architectures", ESIEE, 2006 (6 months)
PhD thesis
Contrôle en ligne des systèmes multiprocesseurs hétérogènes embarqués: élaboration et validation d'une architecture(pdf)
(Online control of embedded heterogeneous multiprocessor systems: elaboration and validation of an architecture)
Nicolas Ventroux
University of Rennes 1, September 2006
Publications
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Multicore and Manycore Architectures (4)
AHDAM: an Asymmetric Homogeneous with Dynamic Allocation Manycore chip(pdf)
C. Bechara, N. Ventroux and D. Etiemble
Facing the Multicore-Challenge II, Springer-Verlag LNCS 6310, Karlsruhe, Germany, September 2011.
SCMP Architecture: An Asymmetric Multiprocessor System-on-Chip for Dynamic Applications(pdf)
N. Ventroux, R. David
ACM International Forum on Next Generation Multicore/Manycore Technologies (IFMT), Saint-Malo, France, 2010.
Les architectures parallèles sur puce. Synthèse des architectures multitâches pour les systèmes embarqués (On-chip parallel architecture. Overview of multithreaded architectures for embedded systems) (pdf)
N. Ventroux, R. David
Science et technique informatiques, vol. 29, n°3, pp. 345-378, 2010.
Hierarchical Network-on-Chip for Embedded Many-core Architectures(pdf)
A. Guerre, N. Ventroux, R. David, A. Merigot
ACM/IEEE International Symposium on Networks-on-Chip (NOCS), Grenoble, France, May 2010.
Virtual Prototyping (8)
SESAM/Par4All: A Tool for Joint Exploration of MPSoC Architectures and Dynamic Dataflow Code Generation - Best paper award - (pdf)
N. Ventroux, T. Sassolas, A. Guerre, B. Creusillet and R. Keryell
HIPEAC Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), Paris, France, January 2012.
A SystemC TLM Framework for Distributed Simulation of Complex Systems with Unpredictable Communication(pdf)
J. Peeters, N. Ventroux, T. Sassolas and L. Lacassagne
IEEE Conference on Design and Architectures for Signal and Image Processing (DASIP), Tampere, Finland, November 2011.
A TLM-based Multithreaded Instruction Set Simulator for MPSoC Simulation Environment(pdf)
C. Bechara, N. Ventroux and D. Etiemble
International Workshop on Rapid Simulation and Performance Evaluation: Methods and Tools (RAPIDO), Crete, Greece, January 2011.
SESAM: an MPSoC Simulation Environment for Dynamic Application Processing(pdf)
N. Ventroux, A. Guerre, T. Sassolas, L. Moutaoukil, G. Blanc, C. Bechara and R. David
IEEE International Conference on Embedded Software and Systems (ICESS), Bradford, UK, 2010.
SESAM Extension For Fast MPSoC Architectural Exploration And Dynamic Streaming Application(pdf)
N. Ventroux, T. Sassolas, R. David, G. Blanc, A. Guerre, C. Bechara
IEEE/IFIP International Conference on VLSI and System-on-Chip (VLSI-SoC), Madrid, Spain, 2010.
Towards a Parameterizable Cycle-Accurate ISS in ArchC(pdf)
C. Bechara, N. Ventroux, D. Etiemble
ACS/IEEE International Conference on Computer Systems and Applications (AICCSA), Hammamet, Tunisia, May 2010.
High Level Power and Energy Exploration using ArchC(pdf)
T. Gupta, C. Bertolini, O. Heron, N. Ventroux, T. Zimmer, F. Marc
IEEE International Symposium on Computer Architecture and High Performance Computing (SBAC-PAD), Petrópolis, Brazil, October 2010.
Approximate-Timed Transactional Level Modeling for MPSoC Exploration: a Network-on-Chip Case Study(pdf)
A. Guerre, N. Ventroux, R. David, A. Merigot
IEEE EUROMICRO Conference on Digital System Design (DSD), Patras, Greece, August. 2009.
Multicore Scheduling Strategies (4)
Comparison of different thread scheduling strategies for Asymmetric Chip MultiThreading architectures in embedded systems(pdf)
C. Bechara, N. Ventroux and D. Etiemble
Euromicro Conference on Digital System Design Architectures, Methods and Tools (DSD), Oulu, Finland, September 2011.
A Power-Aware Online Scheduling Algorithm for Streaming Applications in Embedded MPSoC(pdf)
T. Sassolas, N. Ventroux, N. Boudouani, G. Blanc
Lecture Notes in Computer Science, 2011, Volume 6448, Integrated Circuit and System Design, Power and Timing Modeling, Optimization, and Simulation (PATMOS), Pages 1-10, Grenoble, France, 2010.
Low Complex Task Scheduling Algorithms for Hierachical Embedded Many-Core Architectures and Dynamic Applications(pdf)
A. Guerre, N. Ventroux, R. David, A. Merigot
IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN), Innsbrück, Austria, February 2010.
A low complex scheduling algorithm for multi-processor system-on-chip(pdf)
N. Ventroux, F. Blanc and D. Lavenier
IASTED International Conference on Parallel and Distributed Computing and Networks (PDCN), Innsbrück, Austria, February 2005.
Reliability (10)
On the simulation of HCI-induced variations of IC timings at high level
O. Heron, C. Bertolini, C. Sandionigi, N. Ventroux, F. Marc
Journal of Electronic Testing: Theory and Applications (JETTA), 2013.
Relation between HCI-induced performance degradation and applications in a RISC processor(pdf)
C. Bertolini, O. Heron, N. Ventroux and F. Marc
IEEE International On-Line Testing Symposium (IOLTS), Sitges, Spain, June 2012.
Impact of Power Consumption and Temperature on Processor Lifetime Reliability(pdf)
T. Gupta, O. Heron, N. Ventroux, T. Zimmer, F. Marc and C. Bertolini
Journal of Low Power Electronics (JOLPE), Vol. 8, N°1, pp.83-94, February 2012.
Impact of the application activity on intermittent faults in embedded systems(pdf)
J. Guilhemsang, O. Heron, N. Ventroux, A. Giulieri
IEEE VLSI Test Symposium (VTS), Dana Point, California, USA, May 2011.
System Level Analysis and Accurate Prediction of Electromigration(pdf)
T. Gupta, O. Heron, N. Ventroux, T. Zimmer, F. Marc and C. Bertolini
European Workshop on CMOS Variability (VARI), Grenoble, France, May 2011.
RAAPS: Reliability Aware ArchC based Processor Simulator(pdf)
T. Gupta, C. Bertolini, O. Heron, N. Ventroux, T. Zimmer, F. Marc
IEEE International Integrated Reliability Workshop (IIRW), poster session, Lake Tahoe (USA), October 2010.
Analysis of On-Line Self-Testing Policies for Real-Time Embedded Multiprocessors in DSM Technologies(pdf)
O. Heron, J. Guilhemsang, N. Ventroux, A. Giulieri
IEEE International On-Line Testing Symposium (IOLTS), Corfu, Greece, July 2010.
On-line pseudo-periodic testing for embedded multiprocessor(pdf)
J. Guilhemsang, O. Heron, N. Ventroux, A. Giulieri
IEEE European Test Symposium (ETS), Prague, Czech Republic, May 2010.
Emphasis on the existence of intermittent faults in embedded systems(pdf)
J. Guilhemsang, O. Heron, N. Ventroux, A. Giulieri
IEEE Workshop on Defect and Data Driven Testing (D3T), Austin, USA, October 2010.
Effects of Various Applications on Relative LifeTime of Processor Cores(pdf)
T. Gupta, O. Heron, N. Ventroux, T. Zimmer, F. Marc, C. Bertolini
IEEE International Integrated Reliability Workshop (IIRW), pp.132-135, poster session, Lake Tahoe (USA), October 2009.
Stereovision and Image Processing (2)
Stereovision-based 3D obstacle detection for automotive safety driving assistance(pdf)
N. Ventroux, R. Schmit, F. Pasquet, P-E. Viel and S. Guyetant
IEEE International Conference on Intelligent Transportation Systems (ITSC), St. Louis, Missouri (USA), October 2009.
Rapid prototyping for an optimized MPEG-4 decoder implementation over a parallel heterogeneous architecture(pdf)
N. Ventroux, J.F. Nezan, M. Raulet and O. Déforges
IEEE International Conference on Acoustics, Speech and Signal Processing (ICASSP), Hong-Kong, April 2003.
Multithreaded, reconfigurable and auto-adaptive Architectures (3)
A Small Footprint Interleaved Multithreaded Processor for Embedded Systems(pdf)
C. Bechara, A. Berhault, N. Ventroux, S. Chevobbe, Y. Lhuillier, R. David and D. Etiemble
IEEE International Conference on Electronics, Circuits, and Systems (ICECS), Beirut, Lebanon, December 2011.
An Auto-Adaptative Reconfigurable Architecture for the Control(pdf)
N. Ventroux, S. Chevobbe, F. Blanc and T. Collette
Asia-Pacific Computer Systems Architecture Conference (ACSAC), Springer-Verlag LNCS 3189, pp. 72-87, Beijing, China, September 2004.
RAMPASS: Reconfigurable And Advanced Multi-Processing Architecture for future Silicon Systems(pdf)
S. Chevobbe, N. Ventroux, F. Blanc and T. Collette
International Conference on Embedded Computer Systems: Architectures, MOdeling and Simulation (SAMOS), Springer-Verlag LNCS 3133, pp. 20-29, Samos, Greece, July 2003.
Patents (5)
Method for selecting a resource from a plurality of processing resources such that the likely time lapses before failure evolve in a substantially identical manner(link)
WO/2011/083123
O. Heron, J. Guilhemsang, T. Gupta, N. Ventroux
Device for managing data buffers in a memory space divided into a plurality of memory elements(link)
WO/2010/046355
R. David, N. Ventroux
System comprising a plurality of processing units making it possible to execute tasks in parallel by mixing the mode of execution of control type and mode of execution of data flow type(link)
WO/2009/077429
F. Blanc, S. Louise, V. David, R. David, N. Ventroux, T. Collette
Method and system for conducting intensive multitask and multiflow calculation in real-time(link)
WO/2007/051935
R. David, V. David, N. Ventroux, T. Collette
Task processing scheduling method and device for implementing same(link)
WO/2006/021713
N. Ventroux, S. Chevobbe, F. Blanc, T. Collette
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